1. Technical Field
Embodiments of the invention relate generally to video/graphics front-ends and more specifically to a method and system for input voltage droop compensation in video/graphics front-end systems.
2. Discussion of Prior Art
Video/graphics front-ends generally refer to the analog circuits used for processing and converting input analog signals (graphics or video signals as the case maybe) to digital signals. To provide different DC voltages between the signal and on the chip, a DC-bypass capacitor is used off the chip. Presence of this bypass capacitor typically imposes constraints on the driving-point impedance offered by the on-chip circuits.
DC restoration is a common problem faced in video and graphics front-ends. The video/graphics front-end systems are built using AC coupling which includes a series capacitance. Due to the series capacitance, the DC voltages of the on-chip and off-chip circuits in the system will be different because the capacitor blocks the DC voltages. The action of restoring the DC voltages for the smooth functioning of the system is referred to as DC restoration. A simplified block diagram for a typical video/graphics front-end is illustrated in FIG. 1, 100. The video/graphics front-end system includes a bypass capacitor 105 coupled to an input voltage and to a multiplexer 110. The multiplexer 110 is coupled to a graphics system and a video system. The input network of a graphics system is a sampling circuit 115, while the input network of a video system is a resistive network 120. Since the sampling circuit 115 shares charge with the external bypass capacitor 105, there is a steady degradation in the charge held by the bypass capacitor 105. In other words, the switching network at the input of the graphics front-end can be equivalently modeled as a resistive network. Hence, the problem of DC restoration can be expressed (and solved) in the same terms for both video and graphics front-ends.
Hence, without loss of generality, consider the graphics front-end illustrated in FIG. 2, 200 , together with separate diagrams depicting the sample and hold phases thereof, of an Analog-To-Digital converter (ADC) used in a typical graphics front-end system. During every sampling phase 215, the switches S are closed resulting in an effective sampling circuit 215 in which the sampling capacitor 205 is coupled to the bypass capacitor 105 and becomes charged to the input voltage by sharing charge with the bypass capacitor 105. Depending on the initial charge held by the sampling capacitor 205, there will be some amount of loss of charge in the bypass capacitor 105. Thereafter, switches S are opened and switch H is closed initiating the hold-phase as illustrated by the effective circuit 220. During this phase the charge held by the sampling capacitor 205 is transferred to the feedback capacitor 210 as the sampling capacitor 205 is discharged. Charge on the VGND node is conserved as illustrated in FIG. 2, 200. In the next sampling phase (215), the completely discharged sampling capacitor 205 is coupled back to the bypass capacitor 105 and the process is repeated. In each cycle, a completely discharged sampling capacitor 205 charges itself to the input value by drawing charge from the bypass capacitor 105.
However, as the signal transfer operation proceeds, the charge on the bypass capacitor 105 (which acts as a pseudo voltage-source) faces a gradual reduction due to the ADC operation as explained above. This loss in charge manifests itself as an error in the sampled voltage (relative to the ideal input value), and will appear as an error in the ADC code once the loss is such that the sampled voltage drops by >1 LSB of the ADC. This problem becomes increasingly severe as the resolution of the ADC increases. For example, the actual droop-voltage that can be tolerated is smaller; and in addition, the requirement on the input-referred noise of the ADC demands the use of a larger sampling capacitor 205 which in turn increases the rate at which the input signal droops. Considering typical values of 100 nF for the bypass capacitor 105 and 4 pF for the input sampling capacitor 205 (a 12-bit system will dictate that a sampling capacitor of this order be used), it can be shown that under worst-case conditions where the input signal is white, the signal will droop by 1 LSB for every 6 pixels. To counter this droop, DC restoration is required.
Most of the available ADCs today have a resolution of 8 bits. Relative to a 12-bit ADC, an 8-bit ADC has 1/16th the resolution. And it is apparent that, the input sampling capacitance can be made much smaller. The choice of input sampling capacitor value is based on matching considerations. For example, if the capacitor were to be made 256× smaller, it would contribute the same noise when expressed as a fraction of the LSB, and 32× down-scaling is easily possible). As a result, a droop of 1 LSB occurs for every 3072 pixels. It is thus more than sufficient in these systems if the DC is restored once a line (1024 pixels typically), and consequently, the ADCs employed in today's systems use the blank-level (available every line) to restore the DC. However, with increasing resolution in the ADCs, this is no longer possible.
Hence, there is a need to provide a solution for input voltage droop compensation and reduction in the value of the bypass capacitance in video/graphics front-end systems.